| First cycle degree courses | Second cycle degree courses | Single cycle degree courses |
| School of Engineering | ||
| COMPUTER ENGINEERING | ||
Course unit
COMPUTER ARCHITECTURE (Numerosita' canale 3)
IN05122464, A.A. 2019/20
Information concerning the students who enrolled in A.Y. 2019/20
COMPUTER ARCHITECTURE (Numerosita' canale 3)
IN05122464, A.A. 2019/20
Information concerning the students who enrolled in A.Y. 2019/20
Information on the course unit
| Degree course |
First cycle degree in COMPUTER ENGINEERING IN0508, Degree course structure A.Y. 2011/12, A.Y. 2019/20 |
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|---|---|---|
| Degree course track | Common track | |
| Number of ECTS credits allocated | 9.0 | |
| Type of assessment | Mark | |
| Course unit English denomination | COMPUTER ARCHITECTURE | |
| Department of reference | Department of Information Engineering | |
| Mandatory attendance | No | |
| Language of instruction | Italian | |
| Branch | PADOVA | |
| Single Course unit | The Course unit can be attended under the option Single Course unit attendance | |
| Optional Course unit | The Course unit can be chosen as Optional Course unit |
Lecturers
No lecturer assigned to this course unit
Mutuating
| Course unit code | Course unit name | Teacher in charge | Degree course code |
|---|---|---|---|
| IN05122464 | COMPUTER ARCHITECTURE (Numerosita' canale 3) | -- | IN0507 |
ECTS: details
| Type | Scientific-Disciplinary Sector | Credits allocated | |
|---|---|---|---|
| Basic courses | INF/01 | Computer Science | 1.0 |
| Basic courses | ING-INF/05 | Data Processing Systems | 8.0 |
Course unit organization
| Period | Second semester |
|---|---|
| Year | 1st Year |
| Teaching method | frontal |
| Type of hours | Credits | Teaching hours |
Hours of Individual study |
Shifts |
|---|---|---|---|---|
| Lecture | 9.0 | 72 | 153.0 | No turn |
| Start of activities | 02/03/2020 |
|---|---|
| End of activities | 12/06/2020 |
| Show course schedule | 2019/20 Reg.2011 course timetable |
Examination board
| Board | From | To | Members of the board |
|---|---|---|---|
| 36 A.A. 2019/2020 | 01/10/2018 | 15/03/2020 |
SILVESTRI
FRANCESCO
(Presidente)
COMIN MATTEO (Membro Effettivo) FANTOZZI CARLO (Supplente) PUCCI GEPPINO (Supplente) |
| 35 A.A. 2019/2020 | 01/10/2019 | 15/03/2021 |
COMIN
MATTEO
(Presidente)
SILVESTRI FRANCESCO (Membro Effettivo) CONGIU SERGIO (Supplente) FERRARI CARLO (Supplente) PIZZI CINZIA (Supplente) VANDIN FABIO (Supplente) |
| 33 A.A. 2018/2019 (canale 4) | 01/10/2018 | 15/03/2020 |
SILVESTRI
FRANCESCO
(Presidente)
MENEGATTI EMANUELE (Membro Effettivo) COMIN MATTEO (Supplente) CONGIU SERGIO (Supplente) |
| 32 A.A. 2018/2019 (canale 1) | 01/10/2018 | 15/03/2020 |
COMIN
MATTEO
(Presidente)
SILVESTRI FRANCESCO (Membro Effettivo) CONGIU SERGIO (Supplente) MENEGATTI EMANUELE (Supplente) |
| 31 A.A. 2018/2019 (canale 2) | 01/10/2018 | 15/03/2020 |
MENEGATTI
EMANUELE
(Presidente)
COMIN MATTEO (Membro Effettivo) CONGIU SERGIO (Supplente) MORO MICHELE (Supplente) SILVESTRI FRANCESCO (Supplente) |
| 30 A.A. 2018/2019 (canale 3) | 01/10/2018 | 15/03/2020 |
CONGIU
SERGIO
(Presidente)
COMIN MATTEO (Membro Effettivo) MENEGATTI EMANUELE (Supplente) SILVESTRI FRANCESCO (Supplente) |
| Prerequisites: | Foundations of Computer Science. |
| Target skills and knowledge: | Knowledge and understanding of the main functions of a computer architecture
Knowledge and understanding of the main techniques to organize a computer architecture Ability to develop simple assembly programs using the ARM architecture. |
| Examination methods: | The final exam consists of a written test and an oral examination. The oral examination can be replaced by passing the two intermediate tests. |
| Assessment criteria: | Student assessment is based on the knowledge and understanding of the concepts and methodologies taught in the course, and on the ability to apply them to solve specific problems. |
| Course unit contents: | • Representation of numeric information: representation of natural numbers, integers and rational numbers; two complement, floating point.
• Logic circuits: combinatorial and sequential circuits. • Computer organization: datapath; main memory; control unit; arithmetic and logic unit; input/output devices. • Computer architecture: machine instructions; addressing methods; calling subroutines; dynamic memory allocation. • Introduction to ARM architecture: organization; coding in ARM assembly. • Compiling a program: from source code to the executable code; compiling; assembler; linker. • Interrupt systems: context switch; interrupt identification; external and software interrupts. • Memory organization: cache memory; virtual memory; memory mapping and management unit (MMU); direct memory access (DMA). • Advanced techniques for computer organization: pipelining; branch prediction; speculation; out of order execution; hardware accelerators; multicore. • Computer performance: measuring computer performance; impact of hardware organization on performance. |
| Planned learning activities and teaching methods: | The course consists of lectures in the classroom and exercises in the computer laboratory. Exercises in the laboratory target the ARM architecture and some advanced concepts (e.g., interrupt, DMA, cache). |
| Additional notes about suggested reading: | Studying material includes the adopted textbook and other documents available in Moodle (slides, ARM manuals,…). |
| Textbooks (and optional supplementary readings) |
|
