| First cycle degree courses | Second cycle degree courses | Single cycle degree courses |
| School of Science | ||
| COMPUTER SCIENCE | ||
Course unit
COMPUTER ARCHITECTURE
SC01122464, A.A. 2018/19
Information concerning the students who enrolled in A.Y. 2018/19
COMPUTER ARCHITECTURE
SC01122464, A.A. 2018/19
Information concerning the students who enrolled in A.Y. 2018/19
Information on the course unit
| Degree course |
First cycle degree in COMPUTER SCIENCE SC1167, Degree course structure A.Y. 2011/12, A.Y. 2018/19 |
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|---|---|---|
| Number of ECTS credits allocated | 8.0 | |
| Type of assessment | Mark | |
| Course unit English denomination | COMPUTER ARCHITECTURE | |
| Website of the academic structure | http://informatica.scienze.unipd.it/2018/laurea | |
| Department of reference | Department of Mathematics | |
| Mandatory attendance | No | |
| Language of instruction | Italian | |
| Branch | PADOVA | |
| Single Course unit | The Course unit can be attended under the option Single Course unit attendance | |
| Optional Course unit | The Course unit can be chosen as Optional Course unit |
Lecturers
| Teacher in charge | ALESSANDRO SPERDUTI | INF/01 | |
|---|---|---|---|
| Other lecturers | SILVIA CRAFA | INF/01 | |
| NICOLO' NAVARIN | INF/01 |
ECTS: details
| Type | Scientific-Disciplinary Sector | Credits allocated | |
|---|---|---|---|
| Basic courses | INF/01 | Computer Science | 8.0 |
Course unit organization
| Period | First semester |
|---|---|
| Year | 1st Year |
| Teaching method | frontal |
| Type of hours | Credits | Teaching hours |
Hours of Individual study |
Shifts |
|---|---|---|---|---|
| Practice | 2.0 | 20 | 30.0 | No turn |
| Laboratory | 1.0 | 10 | 15.0 | No turn |
| Lecture | 5.0 | 40 | 85.0 | No turn |
| Start of activities | 01/10/2018 |
|---|---|
| End of activities | 18/01/2019 |
| Show course schedule | 2018/19 Reg.2011 course timetable |
Examination board
| Board | From | To | Members of the board |
|---|---|---|---|
| 9 a.a 2018/2019 | 01/10/2018 | 20/02/2020 |
SPERDUTI
ALESSANDRO
(Presidente)
CRAFA SILVIA (Membro Effettivo) AIOLLI FABIO (Supplente) NAVARIN NICOLO' (Supplente) PALAZZI CLAUDIO ENRICO (Supplente) |
| 8 a.a. 2017/2018 | 01/10/2017 | 20/02/2019 |
SPERDUTI
ALESSANDRO
(Presidente)
AIOLLI FABIO (Membro Effettivo) CRAFA SILVIA (Membro Effettivo) NAVARIN NICOLO' (Membro Effettivo) PALAZZI CLAUDIO ENRICO (Membro Effettivo) |
| Prerequisites: | Basic knowledge in mathematics is required, however no prerequisites are need to be admitted to the course. |
| Target skills and knowledge: | The aim of the course is to enable students to acquire basic functional and technological knowledge regarding computer architectures when considered in isolation from a computer network. Practical exercises in a computer lab will allow students to deepen their knowledge through the use of simple simulators of CPU, Cache, and Pipeline. |
| Examination methods: | The student must pass a written examination and, if deemed necessary by the teacher, an oral examination. |
| Assessment criteria: | The text of the written exam includes some questions that aim to assess the level of learning reached by the student concerning the concepts taught in the course and the student's ability to perform critical analysis on them. The text also includes problems in which the student is required to reconstruct the operation or the configuration settings of some components of the computer. These problems are designed to assess whether the student has developed the ability to apply the concepts learned during the course.
In the event that the assessment of the written exam appears just below sufficiency, the teacher may choose to supplement the written examination with an oral examination to better assess the level of learning of the student. |
| Course unit contents: | The course will cover the topics listed below:
- Introduction: Evolution of Computers, High-level View of the Structure of a Computer; Structure and Function of the CPU. - Memory Management: Memory and Memory Hierarchies. Cache: Mapping Techniques, Replacement Policies. Cache Simulator. - Devices and Input/Output Management: Input / Output: External Devices, I/O Modules, Programmed I/O, Interrupt-Driven I/O, DMA. - Elements of Combinational and Sequential Circuits, Microprogramming: Boolean Algebra. Logic Gates. Combinational Circuits. Sequential Circuits. Microprogramming. - Arithmetic of Computers: Machine Level, Binary Representation, Arithmetic. - Level Instruction Set and Assembler Language: Assembly language. Characteristics and Functions of Machine Instructions. Types of Operands, Data, Operations. Addressing. Instructions Format. CPU Simulator. - Level Instruction Set: CISC and RISC Architectures, Multicore Processors. - Evaluation and Performance Improvement: Pipeline: General Principles, Ideal Performance, Pipeline Hazards, Techniques for Reducing Pipeline Hazards, MIPS. MIPS Pipeline Simulator. |
| Planned learning activities and teaching methods: | The course consists of lectures and exercises in the computer lab. The exercises in the computer lab allow the students to experiment, under various operating scenarios, with simulators of CPU, Cache and Pipeline. In this way, students can verify experimentally the concepts learned in class and acquire the ability to apply the learned concepts and to perform critical judgment. |
| Additional notes about suggested reading: | Slides presented during the lectures are made available to students as reference material. |
| Textbooks (and optional supplementary readings) |
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