First cycle
degree courses
Second cycle
degree courses
Single cycle
degree courses
School of Engineering
ELECTRONIC ENGINEERING
Course unit
COMPUTER ARCHITECTURE (Numerosita' canale 3)
IN05122464, A.A. 2018/19

Information concerning the students who enrolled in A.Y. 2018/19

Information on the course unit
Degree course First cycle degree in
ELECTRONIC ENGINEERING
IN0507, Degree course structure A.Y. 2011/12, A.Y. 2018/19
N4cn3
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Number of ECTS credits allocated 9.0
Type of assessment Mark
Course unit English denomination COMPUTER ARCHITECTURE
Department of reference Department of Information Engineering
E-Learning website https://elearning.dei.unipd.it/course/view.php?idnumber=2018-IN0507-000ZZ-2018-IN05122464-N4CN3
Mandatory attendance No
Language of instruction Italian
Branch PADOVA
Single Course unit The Course unit can be attended under the option Single Course unit attendance
Optional Course unit The Course unit can be chosen as Optional Course unit

Lecturers
No lecturer assigned to this course unit

Mutuated
Course unit code Course unit name Teacher in charge Degree course code
IN05122464 COMPUTER ARCHITECTURE (Numerosita' canale 3) -- IN0513
IN05122464 COMPUTER ARCHITECTURE (Numerosita' canale 3) -- IN0508

ECTS: details
Type Scientific-Disciplinary Sector Credits allocated
Basic courses INF/01 Computer Science 1.0
Basic courses ING-INF/05 Data Processing Systems 8.0

Course unit organization
Period Second semester
Year 1st Year
Teaching method frontal

Type of hours Credits Teaching
hours
Hours of
Individual study
Shifts
Lecture 9.0 72 153.0 No turn

Calendar
Start of activities 25/02/2019
End of activities 14/06/2019
Show course schedule 2019/20 Reg.2011 course timetable

Examination board
Board From To Members of the board
34 BONFRATE 30/05/2019 17/09/2019 COMIN MATTEO (Presidente)
BOMBI FRANCESCO (Membro Effettivo)
33 A.A. 2018/2019 (canale 4) 01/10/2018 15/03/2020 SILVESTRI FRANCESCO (Presidente)
MENEGATTI EMANUELE (Membro Effettivo)
COMIN MATTEO (Supplente)
CONGIU SERGIO (Supplente)
32 A.A. 2018/2019 (canale 1) 01/10/2018 15/03/2020 COMIN MATTEO (Presidente)
SILVESTRI FRANCESCO (Membro Effettivo)
CONGIU SERGIO (Supplente)
MENEGATTI EMANUELE (Supplente)
31 A.A. 2018/2019 (canale 2) 01/10/2018 15/03/2020 MENEGATTI EMANUELE (Presidente)
COMIN MATTEO (Membro Effettivo)
CONGIU SERGIO (Supplente)
MORO MICHELE (Supplente)
SILVESTRI FRANCESCO (Supplente)
30 A.A. 2018/2019 (canale 3) 01/10/2018 15/03/2020 CONGIU SERGIO (Presidente)
COMIN MATTEO (Membro Effettivo)
MENEGATTI EMANUELE (Supplente)
SILVESTRI FRANCESCO (Supplente)
28 A.A. 2017/2018 01/10/2017 15/03/2019 COMIN MATTEO (Presidente)
RODA' ANTONIO (Membro Effettivo)
FANTOZZI CARLO (Supplente)
MENEGATTI EMANUELE (Supplente)
SILVESTRI FRANCESCO (Supplente)

Syllabus
Prerequisites: Foundations of Computer Science.
Target skills and knowledge: Knowledge and understanding of the main functions of a computer architecture
Knowledge and understanding of the main techniques to organize a computer architecture
Ability to develop simple assembly programs using the ARM architecture.
Examination methods: The final exam consists of a written test and an oral examination. The oral examination can be replaced by passing the two intermediate tests.
Assessment criteria: Student assessment is based on the knowledge and understanding of the concepts and methodologies taught in the course, and on the ability to apply them to solve specific problems.
Course unit contents: • Representation of information: representation of natural numbers, integers and rational numbers; two complement, floating point; repreentation of text. audio, images, video.
• Logic circuits: combinatorial and sequential circuits.
• Computer organization: datapath; main memory; control unit; arithmetic and logic unit; input/output devices.
• Computer architecture: machine instructions; addressing methods; calling subroutines; dynamic memory allocation.
• Introduction to ARM architecture: organization; coding in ARM assembly.
• Compiling a program: from source code to the executable code; compiling; assembler; linker.
• Interrupt systems: context switch; interrupt identification; external and software interrupts.
• Memory organization: cache memory; virtual memory; memory mapping and management unit (MMU); direct memory access (DMA).
• Advanced techniques for computer organization: pipelining; branch prediction; speculation; out of order execution; hardware accelerators; multicore.
• Computer performance: measuring computer performance; impact of hardware organization on performance.
Planned learning activities and teaching methods: The course consists of lectures in the classroom and exercises in the computer laboratory. Exercises in the laboratory target the ARM architecture and some advanced concepts (e.g., interrupt, DMA, ...).
Additional notes about suggested reading: Studying material includes the adopted textbook and other documents available in Moodle (slides, ARM manuals,…)
Textbooks (and optional supplementary readings)
  • Stallings, William, Computer organization and architecture: designing for performance - tenth edition. --: Pearson education, 2016. Testo di riferimento del corso Cerca nel catalogo
  • Patterson, Hennessy, Computer Organization and Design ARM Edition: The Hardware Software Interface. --: Morgan Kaufmann, 2017. Testo per consultazione Cerca nel catalogo
  • Congiu, Sergio, Architettura degli elaboratoriorganizzazione dell'hardware e programmazione in linguaggio assembly. --: Patron, 2012. Testo per consultazione Cerca nel catalogo