First cycle
degree courses
Second cycle
degree courses
Single cycle
degree courses
School of Engineering
ELECTRONIC ENGINEERING
Course unit
DIGITAL ELECTRONICS SYSTEMS
INL1001826, A.A. 2016/17

Information concerning the students who enrolled in A.Y. 2015/16

Information on the course unit
Degree course First cycle degree in
ELECTRONIC ENGINEERING
IN0507, Degree course structure A.Y. 2011/12, A.Y. 2016/17
N0
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Number of ECTS credits allocated 9.0
Type of assessment Mark
Course unit English denomination DIGITAL ELECTRONICS SYSTEMS
Department of reference Department of Information Engineering
E-Learning website https://elearning.dei.unipd.it/course/view.php?idnumber=2016-IN0507-000ZZ-2015-INL1001826-N0
Mandatory attendance No
Language of instruction Italian
Branch PADOVA
Single Course unit The Course unit can be attended under the option Single Course unit attendance
Optional Course unit The Course unit can be chosen as Optional Course unit

Lecturers
Teacher in charge DANIELE VOGRIG ING-INF/01

ECTS: details
Type Scientific-Disciplinary Sector Credits allocated
Core courses ING-INF/01 Electronics 9.0

Course unit organization
Period Second semester
Year 2nd Year
Teaching method frontal

Type of hours Credits Teaching
hours
Hours of
Individual study
Shifts
Lecture 9.0 72 153.0 No turn

Calendar
Start of activities 27/02/2017
End of activities 09/06/2017
Show course schedule 2019/20 Reg.2011 course timetable

Examination board
Board From To Members of the board
13 A.A. 2019/2020 01/10/2019 15/03/2021 GERARDIN SIMONE (Presidente)
VOGRIG DANIELE (Membro Effettivo)
BEVILACQUA ANDREA (Supplente)
CESTER ANDREA (Supplente)
GEROSA ANDREA (Supplente)
NEVIANI ANDREA (Supplente)
11 A.A. 2018/2019 01/10/2018 15/03/2020 GERARDIN SIMONE (Presidente)
VOGRIG DANIELE (Membro Effettivo)
BEVILACQUA ANDREA (Supplente)
CESTER ANDREA (Supplente)
GEROSA ANDREA (Supplente)
NEVIANI ANDREA (Supplente)
10 A.A. 2017/2018 01/10/2017 15/03/2019 GERARDIN SIMONE (Presidente)
VOGRIG DANIELE (Membro Effettivo)
CESTER ANDREA (Supplente)
GEROSA ANDREA (Supplente)
NEVIANI ANDREA (Supplente)
PACCAGNELLA ALESSANDRO (Supplente)
9 A.A. 2016/2017 01/10/2016 15/03/2018 VOGRIG DANIELE (Presidente)
GEROSA ANDREA (Membro Effettivo)
BEVILACQUA ANDREA (Supplente)
CESTER ANDREA (Supplente)
GERARDIN SIMONE (Supplente)
MENEGHINI MATTEO (Supplente)
NEVIANI ANDREA (Supplente)
ZANONI ENRICO (Supplente)
8 A.A. 2015/2016 01/10/2015 15/03/2017 VOGRIG DANIELE (Presidente)
BEVILACQUA ANDREA (Membro Effettivo)
CESTER ANDREA (Supplente)
GEROSA ANDREA (Supplente)
MENEGHESSO GAUDENZIO (Supplente)
MENEGHINI MATTEO (Supplente)

Syllabus
Target skills and knowledge: Acquire knowledge at the functional level of the digital systems and of the signal processing techniques for analysis and synthesis of such systems.
Course unit contents: Base-2 algebra: conversion methods, elementary operations, fundamental codes (Gray, BCD, ASCII). Boolean algebra, theorems of consensus and De Morgan. Truth tables and logic functions fundamental (AND, NAND, OR, NOR, XOR). Synthesis of combinational logic functions with Karnaugh maps and methods of minimization. Introduction to circuit realization of logic functions. CMOS: noise margins and dynamic behavior. TTL family: definition and voltage levels. Logic blocks fundamental coder, encoders, multiplexers, demultiplexers, parity generators and comparators. Basic types of memories (ROM, EPROM, EEPROM, RAM). Programmable logic (PLA, PLD, CPLD and FPGA). Addition and multiplication. Synthesis of synchronous and asynchronous sequential logic systems. Counters and shift register.
Textbooks (and optional supplementary readings)